Field of the Invention
The invention is related to computing systems and more particularly to memory systems of computing systems.
Description of the Related Art
In a typical computing system, a memory system is designed with a goal of low latency experienced by a processor when accessing arbitrary units of data. In general, the memory system design leverages properties known as temporal locality and spatial locality. Temporal locality refers to multiple accesses of specific memory locations within a relatively small time period. Spatial locality refers to accesses of relatively close memory locations within a relatively small time period.
Typically, temporal locality is evaluated in terms of a granularity smaller than that of a next level in a memory hierarchy. For example, a cache captures a repeated access of blocks (e.g., 64 Bytes (B)), which is smaller than the storage granularity of main memory (e.g., 4 Kilobyte (KB) pages). Spatial locality is typically captured by storing quantities of data slightly larger than a requested quantity in order to reduce memory access latency in the event of sequential access. For example, a cache is designed to store 64B blocks, although a processor requests one to eight Bytes at a time. Meanwhile, the cache requests 64B at a time from a memory, which stores pages of 4 KB contiguous portions.
Typical memory migration techniques have the goal of further reducing the latency of memory accesses by moving contents of main memory into page caches of a requesting coherence domain in response to individual memory accesses. In general, those techniques rely on software and require either user interception or introduce substantial overhead during migration. Accordingly, improved memory migration techniques are desired.